Honored Contributori'm a student and recently i work on quartus,
i created a multilplier foloating point and i change the time costrint; why varyng the costraint the resurces do not change? example: clk= 1 ns aluts=629 clk=10 ns aluts=629
Honored Contributorchanging the time constraints wont change resource usage. Usually, it just checks that the fitted design can meet your specified timing. If it doesnt meet timing, you can make it try and refit.
To change the resource usage, you have to change the top level design.Honored Contributorresources do not vary because sitetizzatore does not consider the file.sdc or because the costraint does not affect the number of aluts?
it seems strange that the project with a clk = 1GHz and a clk= 100 MHz, uses the same resources. I would like to understand.Honored ContributorIf you look, I suspect that the 1GHz spec failed to meet timing, as even the top FPGAs struggle to get past 300Mhz without serious considerations given to pipelining in the origional source code.
How do you expect the synthesisor to change your design based on timing specs?Honored ContributorI made the same project on xilinx and the resurces vary.
changing the options of xilinx Synthesis and setting "optmize area" the number of LUTs used varies. why this difference? sorry for my english and thanks for attentionHonored Contributorthats not a surprise, as "optimise area" has nothing to do with the timing specifications. You can do the same thing in altera with switches on individual bits of IP.
Honored ContributorWhat do you mean by the switch on bit IP..... sorry for my insistence but i want understand?
Honored Contributorwhen generating some IP cores in the megawizard, you have the option to build it for "speed" or "area". This is really just a paramater at the top level of the code.
