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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

synthesis System verilog design

Hi there, I am a new user in Quartus II and hope that will gain some help here. I wish to synthesis a System Verilog design using Quartus II 6.0. Do anyone have a tutorial on that? I ve tr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The Quartus top level entity must be the name of the top module not the name of its file. e.g. if the file "Lab1.v" starts with:

"module part1 (SW, LEDR);"

then the top level entity must be "part1" not "Lab1.v"!

Or you can just name the top module the same as its file name to make the problem go away.