synthesis System verilog design

With Quartus-II 7.1 (web-edition), I've noticed that if you have *any* coding or structural errors in your RTL-files, Quartus-II sometimes produces bogus/fake error-messages.

For example, I had 10 Systemverilog RTL files in my design. They simulated fine in Modelsim 6.2g PE Student Edition, but nevertheless contained some non-synthesizeable coding errors. When I ran the files through Quartus-II, Quartus-II printed error messages on 2-3 files. But I checked the 2nd and 3rd files -- they looked fine. When I went back and fixed the errors in the first file, all the errors disappeared.

Xilinx's ISE sometimes does the same thing.

Anyway, getting a multi-file project to synthesize, for the first time, is a trial & error process. (Unless you had access to a real linter or formal syntax-checker -- in which case all errors should have already been caught and corrected.)