synthesis System verilog design

There's no difference in the synthesis "process" in the Quartus II software - you just have to create your design files, create a Quartus II project, make sure the top-level entity/module in the code (like the top-level module) is marked in the software, add your files to the project, and compile. (Adding files is required if they are located in a different directory or if the file name does not match the entity/module name, but it's good practice to add them all so you are specifying exactly which files to use).

But of course the syntax is different, and the way the source code is structured (entity/architecture vs module etc.) Perhaps you don't have a top-level module that uses the name you specified as the top-level entity in the project?