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Altera_Forum's avatar
Altera_Forum
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18 years ago

synthesis System verilog design

Hi there, I am a new user in Quartus II and hope that will gain some help here. I wish to synthesis a System Verilog design using Quartus II 6.0. Do anyone have a tutorial on that? I ve tr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Thanks for your reply RYSC. I just wondering whether the process of synthesis a System verilog design is the same as the process for VHDL design?

I ve tried to synthesis one of my VHDL design with the same process as the System verilog and it was successfully done. So I am wondering whether is there any other extra steps to be carrying out in synthesis System Verilog design?