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Altera_Forum's avatar
Altera_Forum
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18 years ago

synthesis System verilog design

Hi there, I am a new user in Quartus II and hope that will gain some help here. I wish to synthesis a System Verilog design using Quartus II 6.0. Do anyone have a tutorial on that? I ve tr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Have you explicitly added the verilog file with a gen_reg module to the project? Might it have a capital letter? (Verilog is case-sensitive). Can't think of much else. You might want to file an SR.