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Altera_Forum's avatar
Altera_Forum
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18 years ago

synthesis System verilog design

Hi there, I am a new user in Quartus II and hope that will gain some help here. I wish to synthesis a System Verilog design using Quartus II 6.0. Do anyone have a tutorial on that? I ve tr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Is gen_reg the name of the project you created, or is it the top-level module in your design? If the top-level module isn't the project name, you need to explicitly tell Quartus otherwise. If you go to Assignments -> Settings -> General, you can change the name of the top-level module/entity of that project. You may have to then explicitly add the files, too. (Project -> Add Files)