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Altera_Forum
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9 years ago

Synthesis support for SystemVerilog files in Quartus Prime Version 16.0.0

Hi all, I am trying to synthesize a SystemVerilog (.sv) file in Quartus Prime Version 16.0.0. I get the following error while using "for" statements without the explicit "generate" stateme...
Altera_Forum's avatar
Altera_Forum
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9 years ago

The handbook for Q16.1 prime pro talks about enhanced SV support, but you need a pro licence.