synthesis problem when read a memory content

Thank you so much. I learn a lot from your explanation. It is a bit triky that the coding style of HDL is very important becase it relates to the hardware.

I will try to use a state machine, like

always(posedge CLK) begin

.....

end

always(*) begin

case()

...

put mem[] in four cases here

...

endcase

end

I hope it will work. By the way, do we need to initial the memory to all 0 to avoid potential problems?