synthesis problem when read a memory content

Depends on. The shown expression tries to read four different memory locations at once, I presume under the control of an edge sensitive always block.

If you write a similar construct in a C program, the compiler reads the memory sequentially. But HDL is a hardware descriptions language, the design compiler synthesizes a hardware that can perform the requested action in one clock cycle. Because it's imposssible in FPGA block RAM, the memory structure will be built in register cells.

The only chance to implement the intended operation in a RAM compatible way is to serialize it, reading one or maximal two (utilizing the said dual-port RAM feature) memory locations per clock cycle. It's unlikely that a simple case strcuture as such will achieve it, you have to organize a sequential access, e.g. using a state machine.

In other words, there's no simple general solution. It depends on the problem and probably involves restructuring of the data processing.