synthesis problem when read a memory content

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You want us to guess what's not working as intended? Obviously it can't infer RAM. Can you guess why?

To give a hint, embedded RAM can only access one memory location at a time (in one clock cycle), maximum two if utilizing the dual-port feature.

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Thank for your reply. You are right. I think I am still not get used to HDL. So can I use a "case" statement and include the above mem[] respectively? Will that synthesis correctly? Thank you.