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Altera_Forum's avatar
Altera_Forum
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18 years ago

synthesis instability

How is possible that the same design, synthetized different times without errors, sometimes on the FPGA correctly run and sometimes no its completly locked? What could be the possible causes? I'm using a stratix2 with quartus 6.0. There are particular structures that quartus cannot synthetized? Thanks a lot!:o

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    I'm trying to change the design and to make a good timing constraints following this made for the ASIC as you have suggested me. I will tell you the results! Thank you to every one! :-)

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    It seems that now the synthesis is ok. I have substitueted the gating and the mux clock with the block control block and set as timing constraints fmax: now all seems working! Thank you very much to all of you!:)