--- Quote Start ---
I have different clocks obtain from a master by divider, gating and so on and so for... and the master clock could be programmed... it's difficult to make good timing constraints. Timing analyzer give me some hold time negative.
--- Quote End ---
It sounds like you are dividing and gating with logic. It is highly preferred that dividing be done with a PLL or clock enable and that gating be done with a clock control block (a dedicated silicon resource available in some device families) or clock enable. Having logic resources (either registers for dividing or LUTs for gating) or even nonglobal routing in the clock path introduces skew if the source and destination register don't have the same clock path (crossing to or from a divided/gated clock domain or between registers in the same domain with nonglobal routing). This clock skew can cause either the clock hold violations you mentioned or clock setup violations.
If you are using the Classic Timing Analyzer, right clock one of the failures in the Clock Hold (or Clock Setup) table and select "List Paths". In the Messages window System tab, press the <Ctrl> key while clicking the plus sign at the left end of the new message to expand everything at once (or just keep clicking plus signs to expand one step at a time). Look at what is happening in the requirement section. Pay particular attention to what is in the clock skew section. Your logic for dividing and gating should be shown in the clock skew section.
I've made other comments about this in "Altera Forums > Tools Related > Quartus II Discussion > PLL Clock Frequency" (
http://www.alteraforum.com/forum/showthread.php?p=1273#post1273). That post has a suggestion to do the dividing with a clock enable (as good as using a PLL, but might require more changes to your source files because you didn't use a clock enable from the beginning) and suggestions in case you do continue to drive your clocks with logic resources.
Honored Contributor
