synthesis instability

Hello,

there is another possibility why the implementation doesn't work in different fits. If the design has different clock domains, take sure, that the signals are synchronized in a correct way. If the clocks are completly unrelated quartus cuts all timing calculations accross the clock boundaries. (Unrelated means, that the clocks are used or derived from different clock input pins.) So if the signals are not synchronized in a correct way, different parts of the logic can get different signal levels of the same signal in the new clock domain.