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Altera_Forum's avatar
Altera_Forum
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18 years ago

synthesis instability

How is possible that the same design, synthetized different times without errors, sometimes on the FPGA correctly run and sometimes no its completly locked? What could be the possible causes? I'm usi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

You also want to make sure that do not have any asynchronous logic in your design. That would cause the condition erratic behavior from route to route. You can check your timing report file for warnings of this nature.

Stan