synthesis instability

It might not be synthesis issues. I have seen this symptom when I have not covered everything in timing closure. Just last week I thought perhaps Quartus was messing up with my state machine, because it had two different states active at the same time. It ended up being the reference clock not staying locked. Reliance on signals across clock boundaries without proper clock domain bridging is another pot-hole that has caused inexplicable symptoms. Not since 2000 have I seen problems I could track back to a synthesis bug.