Synthesis error in Quartus v12 & v11

Here is the code snippet:

reg  sr;
reg  qCtrl;
reg  qDelay;
reg  qTrigA;
reg  qTrigB;
reg  qXfrStart;
reg  qXfrSize;
wire  regAddr = sr;
always @(posedge clk109, posedge reset109) begin
   if(reset109) begin
      qCtrl <= 16'b100;
   end else begin
      if(shiftIn)
         sr <= { sr, dataSync };
      if(rxEnd) begin
         case(regAddr)
            3'd0: qCtrl <= sr;
            3'd1: qDelay <= sr;
            3'd2: qTrigA <= sr;
            3'd3: qTrigB <= sr;
            3'd4: qXfrStart <= sr;
            3'd5: qXfrSize <= sr;
         endcase
         sr <= { 4'b0, stopIndex };
      end
   end
end

The line highlighted in blue is the preset causing the problem. If it's changed to:

qCtrl <= 16'b0;

The problem does not occur. The clock enables shiftIn and rxEnd are mutually exclusive, in case you were wondering.