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Altera_Forum
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13 years ago

Synthesis error in Quartus v12 & v11

There is an apparent synthesis error in Quartus v12, v11 and possibly other versions. I found this by adding an asynchronous preset to a register bit. When this is done that register bit is not prese...
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Altera_Forum
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13 years ago

Please show a code example that allows to reproduce the problem.

If you are feeding both asynchronous set and reset to a DFF, it has to be emulated by a combination of a DFF, XOR gates and latches for most recent FPGA, also Cyclone III. What you describe may be either a real synthesis error or just lack of understanding how Quartus emulates the function at gate level.

An example is shown in this post http://www.alteraforum.com/forum/showthread.php?t=36490