Syntax Error

its not work..same error appear same as usual..here is the lines..

gDelay: counterDelay port map (d, clk, q);

yDelay: counterDelay port map (d, clk, q);

Error (10500): VHDL syntax error at allT.vhd(54) near text "port";  expecting "(", or "'", or "."
Error (10500): VHDL syntax error at allT.vhd(54) near text ";";  expecting ":=", or "<="
Error (10500): VHDL syntax error at allT.vhd(80) near text "port";  expecting "(", or "'", or "."
Error (10500): VHDL syntax error at allT.vhd(80) near text ";";  expecting ":=", or "<="

	architec...
signal d, q : std_logic_vector(3 downto 0);
	
component counterDelay
	port(D : in std_logic_vector(3 downto 0); 
               clk : in std_logic;
		 Q      : out std_logic_vector(3 downto 0));
end component;
begin

library ieee;
use ieee.std_logic_1164.all;
entity counterDelay is
	port(D   : in std_logic_vector(3 downto 0);
		 clk : in std_logic;
		 Q   : out std_logic_vector(3 downto 0));
end counterDelay;
architecture dbehav of counterDelay is
begin
	process(D, clk)
	begin
		if (clk'event AND clk = '1') then
			if D = 15 then
				for i in 1 to 15 loop
					Q <= D;
				end loop;
			elsif D = 3 then
				for i in 1 to 3 loop
					Q <= D;
				end loop;
			end if;
		end if;
	end process;
end dbehav;