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Altera_Forum's avatar
Altera_Forum
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13 years ago

Syntax Error in verilog?

Hey, Im just starting to learn to use Quartus II, and I keep getting a syntax error when I try to compile this at line 3 module mux2to1_8bit(SW, LEDR); input [17:0]SW; wire [7:0]X, [7:0]Y...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Follow the Verilog syntax rules. You can't have multiple range specifications in one net declaration.