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Altera_Forum
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11 years ago

Syncronous counter generating rippled outputs

This thing is driving me crazy. I have been trying to make a synchronous 16 bit divide-by-N counter with schematic entry. I got the logical part working. Two different designs. Both seem to be co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

The main concept of default synchronous design is that an update on Q output is ok as long as new value is available at destination register (after passing through any luts) within 1 clock period and without violating timing window of destination register. This is how fmax is limited. TQ will tell if your fmax is achievable or not.

So read TQ report and don't worry about your visual analysis.