Honored Contributor
Honored ContributorThanks for the reply. I have attempted to attach an image of the timing simulation. The outputs are supposed to change on the rising clock pulse.
I'm thinking you're right because the desired output (TCN) seems valid. It starts to fail around 170 MHz. But with delays like that, it should be failing closer to 100 MHz. At 170MHz, some of the delays are longer than the clock period. The image shows the simulation at 100MHz. Notice how the Q0 output delay is almost the full clock period (10ns). Then it still has to go through the look behind logic to feed the D inputs of the other ff's. More delay. That kind of thing doesn't make sense to me. Is there any possibility that the simulator is flawed? Or my use of it? Anyhow, I guess the thing to do is not worry about it like you said. My physical system clock is only 48MHZ so this circuit should work. Is there a way in quartus to make certain nodes faster? Or some way to mark a node as timing critical so that it isn't routed to the next gate by way of the other side of the chip? https://www.alteraforum.com/forum/attachment.php?attachmentid=10710
