Forum Discussion
Occasional ContributorSYNCHRONIZED RS232 DATA CORRUPTED
I read the code so that you are sampling 1200 Baud UART input at 1200 Hz only. I'd expect oversampling with e.g. factor 8 as any usual UART does. Or did I miss code details?
There's no use of synchronizing Rx at a reduced rate, this can be done with full clock rate, e.g. 50 MHz.
Decoding of UART data at suitable oversampling rate allows to detect start bit falling edge with necessary accuracy and start to sample data bits after 1/2 bit duration.
Occasional ContributorThanks for your reply.
Yes. At first i just synced rx data with 50MHz clock itself but found out also sometimes bytes are corrupted.
FSM and Counter works on 1200Hz, otherwise would need to add some counter ie if i use clock enable at 3600 to sample in the middle only for the counter but fsm must work on high frec if i want to capture start bit accurately i guesss..
Weird thing is simulation works fine jejej
Super Contributorworking simulation doesn't mean much if you don't test different timing relations between clock and data.
Although it can be instructive to design UART from the scratch, it's also a good idea to take a look at one of many existing designs.
- Armando1989Hi FvM
Yep im just doing from scratch for the sake of learning. I know there is a known uart scheme already defined online, also there is IP on quartus offering uart itself
Im working on 2x sampling and capture on middle of the bit.
Thanks- FvMHi,
factor 4 is the minimal oversampling ratio we see in UART design, factor 8 is more commonly used. You play in simulation with relation between sampling clock and RX data and see why factor isn't enough.- Armando1989
Hi FvM
In this current design attached, state machine is working at 50MHz top speed, its duty is just detect the start bit and enable the baudrate generation just then (i guess this was the key part with problem i had before on data sampling missalignement).
The baudrate generator is 2x sampling, here is set for 115200 top rs232 speed. The counter samples at the middle of the bit after start bit. The more complex and maybe "pain to see" part is the capturer way for waking up DONE signal and put it down again before FSM stops the baudrate generation. Since capturer uses the baudrate generator clock enable signal to work....
Solution was combinational and the pulse last just 1/2 50Mhz period so im quite adjusted on hold time constraint for faster models... even it pass the timing analisys.... Maybe that could be enhaced by enlarge the capturing window on baudrate generator to several 50MHz clocks, that will enlarge clock_enable pulse width and allow.
As said, just learning however let me know if consider FSM sampling 50MHz is good enough.
Tested working fine so far at 115200 speed.
Thanks in advance!
