Forum Discussion
Occasional ContributorSYNCHRONIZED RS232 DATA CORRUPTED
I read the code so that you are sampling 1200 Baud UART input at 1200 Hz only. I'd expect oversampling with e.g. factor 8 as any usual UART does. Or did I miss code details?
There's no use of synchronizing Rx at a reduced rate, this can be done with full clock rate, e.g. 50 MHz.
Decoding of UART data at suitable oversampling rate allows to detect start bit falling edge with necessary accuracy and start to sample data bits after 1/2 bit duration.
Super ContributorI read the code so that you are sampling 1200 Baud UART input at 1200 Hz only. I'd expect oversampling with e.g. factor 8 as any usual UART does. Or did I miss code details?
There's no use of synchronizing Rx at a reduced rate, this can be done with full clock rate, e.g. 50 MHz.
Decoding of UART data at suitable oversampling rate allows to detect start bit falling edge with necessary accuracy and start to sample data bits after 1/2 bit duration.
Armando1989Hi FvM
Thanks for your reply.
Yes. At first i just synced rx data with 50MHz clock itself but found out also sometimes bytes are corrupted.
FSM and Counter works on 1200Hz, otherwise would need to add some counter ie if i use clock enable at 3600 to sample in the middle only for the counter but fsm must work on high frec if i want to capture start bit accurately i guesss..
Weird thing is simulation works fine jejej- FvMHi,
working simulation doesn't mean much if you don't test different timing relations between clock and data.
Although it can be instructive to design UART from the scratch, it's also a good idea to take a look at one of many existing designs.- Armando1989Hi FvM
Yep im just doing from scratch for the sake of learning. I know there is a known uart scheme already defined online, also there is IP on quartus offering uart itself
Im working on 2x sampling and capture on middle of the bit.
Thanks
