Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

SXT Error

I'm porting some old Xilinx code to Altera and I'm hitting an error.

When using the SXT function in the following code, I'm receiving an error.

--code

sum_azp_180(16 downto 0) <= (('0' & X"7080") + SXT(az_phase, 17));

--error

Error (10621): VHDL Use Clause error at file.vhd(259): more than one Use Clause imports a declaration of simple name ""+"" -- none of the declarations are directly visible

Error (10784): HDL error at file.vhd(36): see declaration for object ""+""

I have the following libraries included in the vhdl file.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_SIGNED.ALL;

use IEEE.STD_LOGIC_MISC.ALL;

use IEEE.NUMERIC_BIT.ALL;

Any suggestions?

Thanks

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    VHDL is very picky about type safety. The error message is indicating that there are multiple definitions of "+" that can be used to implement the operation.

    It looks like you've included too many packages (and packages that have been superceded in the language). Change the library definitions to:

    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;

    use IEEE.NUMERIC_STD.ALL;

    and then start debugging.

    Cheers,

    Dave