Subtracting from a std_logic_vector

I agree with Tricky. Underflow and overflow occurs naturally when perform add and substract operations. If you perform a simulation with Model Sim you see that "0000" - "0001" gives "1111" ( underflow ). Try the testbench:

uut : entity work.sumador_2

port map(

a => tb_a,

s => tb_s

);

process

begin

wait for 1ms;

for i in 0 to 15 loop

tb_a <= std_logic_vector(to_unsigned(i, 4));

wait for 1ms;

end loop;

assert false

report "Fin de la simulacion"

severity failure;

end process;

Where sumador_2 is:

architecture data_flow of sumador_2 is

begin

s <= std_logic_vector( unsigned(a) - "0001");

end architecture data_flow;