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Altera_Forum
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13 years ago

Subtracting from a std_logic_vector

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; . . . signal count_val : std_logic_vector(5 downto 0) := "000000"; . . ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Over/underflowing is a perfectly normal behavior when using a bit type, and no tool should throw an error (I dont know how you would synthesis a checker for it anyway without specifically building one).

Integer on the other hand will not overflow in simulation, you'll get an error, but on an FPGA it will overflow.