shreyasNew Contributor7 years agoStuck at the Analysis and synthesis stage Hi all, I am trying to synthesize a design which is relatively big with ~ 30k lines of RTL. But the process just get stuck at analysis and synthesis stage. I waited for more than 10 hours but had no...Show More
shreyasNew Contributor7 years agoHiGreat! that worked. Thanks a lot for your help. Problem was with those memory block.
Recent DiscussionsHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorConnection bit order between hierarchyCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: