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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

stronge behavior of case statement

Hi All...I have a very strange behavior of a case statement. In timing simulation, this segment of code:

fifo_ctrl_data: process

begin

wait until clk'event and clk='0';

case sc is

when s1 =>

txmit_dcfifo_wrreq <= '0';

txmit_dcfifo_data <= (others => '0');

when s2 =>

txmit_dcfifo_wrreq <= '0';

txmit_dcfifo_data <= (others => '0');

when s3 =>

txmit_dcfifo_wrreq <= '0';

txmit_dcfifo_data <= (others => '0');

when s4 =>

txmit_dcfifo_wrreq <= '0';

txmit_dcfifo_data <= (others => '0');

when s9 =>

txmit_dcfifo_wrreq <= '1';

txmit_dcfifo_data <= ec_frame(0);

when s10 =>

txmit_dcfifo_wrreq <= '1';

txmit_dcfifo_data <= ec_frame(1);

when s11 =>

txmit_dcfifo_wrreq <= '1';

txmit_dcfifo_data <= ec_frame(2);

when others =>

txmit_dcfifo_wrreq <= '0';

txmit_dcfifo_data <= (others => '0');

end case;

end process;

does not give the same results as this segment of code:

fifo_ctrl_data: process

begin

wait until clk'event and clk='0';

case sc is

when s9 =>

txmit_dcfifo_wrreq <= '1';

txmit_dcfifo_data <= ec_frame(0);

when s10 =>

txmit_dcfifo_wrreq <= '1';

txmit_dcfifo_data <= ec_frame(1);

when s11 =>

txmit_dcfifo_wrreq <= '1';

txmit_dcfifo_data <= ec_frame(2);

when others =>

txmit_dcfifo_wrreq <= '0';

txmit_dcfifo_data <= (others => '0');

end case;

end process;

I tried functional simulation. Both are the same...so anyone can explaine why?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Hi,

    I guess that the compiler wouldn't see the two cases as equivalent since there are more tests when you ask for more and the netlists wouldn't be identical.

    Compiler technology is subject to the choice/limitations of the software designers who may or may not want to make inferrences from the code in the same way you do.

    Another example: The following algorithm will generate three multipliers

    if condition1 multiply a,b

    elsif condition2 multiply a,c

    else multiply a,d end

    to overcome that, use one mult statement and mux inputs.

    kaz
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Can you be more specific - what is the difference in behaviour?

    Also, you don't have the clk on your sensitivity list for the process!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Hi,

    Obviously you need a clocked process as appropriate, I am just talking about the algorithm.

    at each statement of "multiply" the compiler synthesizes a multiplier.

    If on the other hand you mux the input to one multiplier you get one mult for same functionality:

    mult_out <= a * mult_in;

    if condition1 mult_in <= b

    elsif condition2 mult_in <= c

    else mult_in <= d end

    kaz
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Thanks for the reply

    --- Quote Start ---

    Hi Kaz

    Sorry my post was directed at zhangyi17's original post.

    --- Quote End ---