Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

stronge behavior of case statement

Hi All...I have a very strange behavior of a case statement. In timing simulation, this segment of code: fifo_ctrl_data: process begin wait until clk'event and clk='0'; case sc is w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

Obviously you need a clocked process as appropriate, I am just talking about the algorithm.

at each statement of "multiply" the compiler synthesizes a multiplier.

If on the other hand you mux the input to one multiplier you get one mult for same functionality:

mult_out <= a * mult_in;

if condition1 mult_in <= b

elsif condition2 mult_in <= c

else mult_in <= d end

kaz