Stratix4 GX HSSI hspice model simulation problem

Hi,

I'm trying to do simulations with the Stratix4 GX HSSI hspice models.

The sample spice files allwork well, but as soon as I change the instantiation

of the Verilog-A device ( in this case tx_top) from

xtx_top tx_clk tx_highv tx_pre_em_1t[0] tx_pre_em_1t[1] tx_pre_em_1t[2] tx_pre_em_1t[3] tx_pre_em_1t[4] tx_pre_em_2t[0]

+ tx_pre_em_2t[1] tx_pre_em_2t[2] tx_pre_em_2t[3] tx_pre_em_pt[0] tx_pre_em_pt[1] tx_pre_em_pt[2] tx_pre_em_pt[3]

+ tx_siginv_2t tx_siginv_pre tx_slew[0] tx_slew[1] tx_term_sel[0] tx_term_sel[1] tx_term_sel[2] tx_vod_sel[0]

+ tx_vod_sel[1] tx_vod_sel[2] tx_vtt[0] tx_vtt[1] vcceht vccet vid txon_bump txop_bump vss tx_top S=1U

to

xtx1_top tx_clk tx_highv tx_pre_em_1t[0] tx_pre_em_1t[1] tx_pre_em_1t[2] tx_pre_em_1t[3] tx_pre_em_1t[4] tx_pre_em_2t[0]

+ tx_pre_em_2t[1] tx_pre_em_2t[2] tx_pre_em_2t[3] tx_pre_em_pt[0] tx_pre_em_pt[1] tx_pre_em_pt[2] tx_pre_em_pt[3]

+ tx_siginv_2t tx_siginv_pre tx_slew[0] tx_slew[1] tx_term_sel[0] tx_term_sel[1] tx_term_sel[2] tx_vod_sel[0]

+ tx_vod_sel[1] tx_vod_sel[2] tx_vtt[0] tx_vtt[1] vcceht vccet vid txon_bump txop_bump vss tx_top S=1U

I get the error messages

**warning** invalid circuit pathname xtx_top.xtxdrv

**error** invalid node pathname in element cap27

**warning** invalid circuit pathname xtx_top.xtxdrv

**error** invalid node pathname in element cap28

**warning** invalid circuit pathname xtx_top.xtxdrv

**error** invalid node pathname in element cap29

**warning** invalid circuit pathname xtx_top.xtxdrv

**error** invalid node pathname in element cap30

**warning** invalid circuit pathname xtx_top.xtxdrv.xpredrv

**error** invalid node pathname in element cap31

**warning** invalid circuit pathname xtx_top.xtxdrv.xpredrv

**error** invalid node pathname in element cap32

**warning** invalid circuit pathname xtx_top.xtxdrv.xpredrv

**error** invalid node pathname in element cap33

**warning** invalid circuit pathname xtx_top.xtxdrv.xpredrv

**error** invalid node pathname in element cap34

**warning** invalid circuit pathname xtx_top.xtxdrv.xpredrv

**error** invalid node pathname in element cap35

**warning** invalid circuit pathname xtx_top.xtxdrv.xpredrv

**error** invalid node pathname in element cap36

**warning** invalid circuit pathname xtx_top.xtxdrv.xpredrv

**error** invalid node pathname in element cap37

**warning** invalid circuit pathname xtx_top.xtxdrv

**error** invalid node pathname in element cap38

**warning** invalid circuit pathname xtx_top.xtxdrv

**error** invalid node pathname in element cap39

**warning** invalid circuit pathname xtx_top.xtxdrv

**error** invalid node pathname in element cap40

**warning** invalid circuit pathname xtx_top.xtxdrv.xi99b

**error** invalid node pathname in element cap45

**warning** invalid circuit pathname xtx_top.xtxdrv.xi99b

**error** invalid node pathname in element cap46

**warning** invalid circuit pathname xtx_top.xtxdrv.xi99b.x4.x1

**error** invalid node pathname in element cap47

**warning** invalid circuit pathname xtx_top.xtxdrv.xi99a

**error** invalid node pathname in element cap48

**warning** invalid circuit pathname xtx_top.xtxdrv.xi99a

**error** invalid node pathname in element cap49

**warning** invalid circuit pathname xtx_top.xtxdrv.xi99a.x4.x1

**error** invalid node pathname in element cap50

**warning** invalid circuit pathname xtx_top.xtxdrv

**error** invalid node pathname in element cap65

**warning** invalid circuit pathname xtx_top.xtxdrv

....

Is there a workaround to this problem or is this a bug in the encrypted spice files,

which come with this simulation kit. This problem also occurs, when I change the

instantiation of the rx_top device.

Any help is appreciated.

Thanks in advance

Regards

awallrab