Stratix V pin I/O delays

Page 4-41 of the doc you posted list exactly how to do it. Unfortunately Altera does not provide a document that list pin delays for every pin/device combination. You must compile the design with the board deskew option turned on to get the package delays to show up in the pin report.

To get the package delay information, follow these steps:

1. Select the FPGA DQ/DQS Package Skews Deskewed on Board checkbox on the Board Settings tab of

the parameter editor.

2. Generate your IP.

3. Instantiate your IP in the project.

4. Run Analysis and Synthesis in the Quartus Prime software. (Skip this step if you are using an Arria 10

device.)

5. Run the <core_name>_p0_pin_assignment.tcl script. (Skip this step if you are using an Arria 10

device.)

6. Compile your design.

7. Refer to the All Package Pins compilation report, or find the pin delays displayed in the

<core_name>.pin file.