Stratix IV DDR clock constrain problem

Hi friends,

I am working on a DDR project in Stratix IV FPGA. I am using ALTMEMPHY. Now I get a problem that the FPGA cannot work stably. Note that I make a clock constrain for DDR input clock pin and there is a conflict warning for this clock constrain and DDR PHY sdc file. Is this the root cause? And I shall not use this clock input frequency constain in the top sdc file and just use PHY sdc file?

Thanks!