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Altera_Forum
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14 years ago

Stratix III FPGA: Problem using Asynchronous FIFOs

Hi, I’m using a Stratix III FPGA and I have made a design using two interconnected Asynchronous FIFOs and when I launch the Post-Place and route simulation (using Modelsim) it doesn’t work...
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Altera_Forum
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13 years ago

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May you can set up Signaltap to focus on what happens at the start of packet?

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There is a start of a packet I've mentioned before. I trigger on start signal, but also 0x47 is a start byte. All start signals comes up with 0x47.

I could also suffer from data writes to the middle of the packet when fpga powers up, this means, that 0x47 could anywhere, but not at the start place. I will try to do some safety logic here.