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Yes, sorry for misunderstanding before.
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No it was me jumping quick to decisions :)
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Altera says that I should wait a few cycles after reset before asserting wrreq. Maybe this could be an issue?
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There are few warnings about wrreq being active while aclr is. So I may be a good idea to either only reset the fifo at powerup (and real error conditions) and further rely on the FIFO to do what it should do or either to keep reset and wrreq well apart.
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I am triggering on the start signal and my signaltap memory is quite short. According to the results I observe, I believe I get such data corruptions every received packet (packet length = 188 bytes).
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May you can set up Signaltap to focus on what happens at the start of packet?
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