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Altera_Forum
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14 years ago

Stratix III FPGA: Problem using Asynchronous FIFOs

Hi, I’m using a Stratix III FPGA and I have made a design using two interconnected Asynchronous FIFOs and when I launch the Post-Place and route simulation (using Modelsim) it doesn’t work...
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Altera_Forum
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13 years ago

I usually instantiate RAMs and FIFOs directly, without using the MegaWizard. (hence my setting of 5 ...)

Now 8192 words of 9 bits is definitely larger than 8 (or 36).

Is 'aclr' connected and in which clock domain is it generated?

The output stream looks like 3 writes with '0x00' have preceded the '0x47' one. After that the stream is correct.