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Altera_Forum
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14 years ago

Stratix III FPGA: Problem using Asynchronous FIFOs

Hi, I’m using a Stratix III FPGA and I have made a design using two interconnected Asynchronous FIFOs and when I launch the Post-Place and route simulation (using Modelsim) it doesn’t work...
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Altera_Forum
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13 years ago

The parameter block you show is inside a .tdf file, I presume, the 'real' parameters are found in the invocation of that .tdf, one level higher.

For a dcfifo LPM_NUMWORDS must be at least 8 (and preferably a power of 2). I guess that in the case of a dcfifo_mixed_widths as used in your case it must be 32 to guarantee those 8 words at the output side.