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Altera_Forum
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14 years ago

Stratix III FPGA: Problem using Asynchronous FIFOs

Hi, I’m using a Stratix III FPGA and I have made a design using two interconnected Asynchronous FIFOs and when I launch the Post-Place and route simulation (using Modelsim) it doesn’t work...
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Altera_Forum
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13 years ago

What's the fifo depth? it must be at least 8 for a dcfifo to work correctly. For a dcfifo_mixed_widths it may well be the depth on the 'wide' side.

The Design Assistant warning should have been suppressed by the dcfifo-code.