Stratix III FPGA: Problem using Asynchronous FIFOs

The pipeline level should be set to 5. from the 'SCFIFO and DCFIFO Megafunctions User Guide' :

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Specify the number of synchronization stages in the cross clock domain. The value of the RDSYNC_DELAYPIPE parameter relates the synchronization stages from the write control logic to the read control logic, while the WRSNYC_DELAYPIPE parameter relates the synchronization stages from the read control logic to the write control logic. Use these parameters to set the number of synchronization stage if the clocks are not synchronized,

and set the CLOCKS_ARE_SYNCHRONIZED parameter to FALSE.

The actual synchronization stage implemented relates variously to the parameter value assigned, depends on the target device.

For Cyclone II and Stratix II devices and onwards, the values of these parameters are internally reduced by 2. Thus, the default values of 3 for these parameters correspond to a single synchronization stage, a value of 4 results in 2 synchronization stages, and so on. For these devices, choose the value at least of 4 (2 synchronization stages) for metastability protection. See “Metastability Protection and Related Options” on page 15.

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