Stratix III FPGA: Problem using Asynchronous FIFOs

PS: You can ignore those SETUP violation of ACLR in respect to CLK, as long as the reset pulse is longer than 1 clock.

It's the other ones which are hurting you.

You need to look down into the RTL or post mapping schematics, find out which are the first level of synchronization registers and then disable timing checks on them.

I think it will be something like

tcheck_set /tb_fifo/UUT/\fifo_cmp|dcfifo_component|auto_generated|rs_dgwp OFF

But I stress again, it's important that you know what you're doing and only disable checks for the first level of synchronization registers.

If you disable timing checks for other registers, you may just end up hiding other bugs that may exist.