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Altera_Forum
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14 years ago

Stratix III FPGA: Problem using Asynchronous FIFOs

Hi, I’m using a Stratix III FPGA and I have made a design using two interconnected Asynchronous FIFOs and when I launch the Post-Place and route simulation (using Modelsim) it doesn’t work...
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Altera_Forum
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14 years ago

Yes, I’m using two Asynchronous FIFOs with a 5 stage synchronizer, so my option is the b one. Why isn’t it possible to do timing analysis on unrelated clocks? Does it mean I can't do a correct Gate Level Simulation?