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Altera_Forum
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14 years ago

Stratix III FPGA: Problem using Asynchronous FIFOs

Hi, I’m using a Stratix III FPGA and I have made a design using two interconnected Asynchronous FIFOs and when I launch the Post-Place and route simulation (using Modelsim) it doesn’t work...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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My design works in functional simulation, so I'm trying to test it in Gate Level simulation before I introduce it into the board. But it works only in the best case (Fast and 0 ºC) and fails in the others, so it isn't going to work in the FPGA.

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I think it is in the testbench. I have a different style and I don't see immediately how the input signals behave. Maybe you can send be a .qar(with the inputdata.txt file)? I'll take a deeper look then.