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Altera_Forum
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14 years ago

Stratix III FPGA: Problem using Asynchronous FIFOs

Hi, I’m using a Stratix III FPGA and I have made a design using two interconnected Asynchronous FIFOs and when I launch the Post-Place and route simulation (using Modelsim) it doesn’t work...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I get those frequencies using TimeQuest Analyser from Quartus, but when I try to test my design using modelsim (with the .vho and .sdo files) it doesn't work for those frequencies. So, can the frequencies be wrong?

Referring to the sdc file, how can I set the output delays?