Stratix III 3SL150 Holes in Flash

I managed to create a workaround. Several days ago, I tried to instantiate the PFL megacore. I was consistently getting the invalid silicon ID on device 1 error after the bitstream was loaded to the FPGA. This seemed to be to me a problem with the PFL core not recognizing the flash as it is two dies stacked on top of each other with no knowledge of each other. I went ahead and changed the parameters to make it a 256 Mbit flash (512 total on the package), pulled the highest address bit high, regenerated my pof as a 256 Mbit file with changed addressing (user space starting at byte 0x1500000 instead of 0x3500000), and programmed the device according to Altera's directions. This time, verification succeeded, I saw no more unexpected 0xFF gaps in the data, and my OR1200 CPU core now boots.

module stratix_iii_flash_prog_top (
        input         pfl_flash_access_granted,
        input         pfl_nreset,
        output  flash_addr,
        inout   flash_data,
        output        flash_nce,
        output        flash_noe,
        output        flash_nwe,
        output        pfl_flash_access_request,
        output        sram_ncs,
        output        sram_noe
    );
    
    pfl pfl0 (
        .pfl_flash_access_granted(pfl_flash_access_granted),
        .pfl_nreset(pfl_nreset),
        .flash_addr(flash_addr),
        .flash_data(flash_data),
        .flash_nce(flash_nce),
        .flash_noe(flash_noe),
        .flash_nwe(flash_nwe),
        .pfl_flash_access_request(pfl_flash_access_request)
    );
    
    assign flash_addr = 1'b1;
    assign sram_ncs = 1'b1;
    assign sram_noe = 1'b1;
endmodule