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GMcCa2's avatar
GMcCa2
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Stratix 10 HPS DDR4 EMIF placement error

Hello, I'm trying to compile a design for the Terasic S10 SOM (https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=248&No=1229&PartNo=1#contents). They provide a GHRD whi...
Hdl
  • KianHinT_altera's avatar
    KianHinT_altera
    2 years ago

    Hi ,

    Sorry for the delay in getting back, was scrutinizing the pins with the team and doing testing on the Quartus fitter

    To resolve the fitter error on the IO lane and tile, you will need to remove the pin assignment CLK_50_B2L in pin planner and let the fitter reassign it automatically (alternatively edit the qsf file, and remove the constraint "set_location_assignment PIN_BA27 -to CLK_50_B2F"

    This is some others restrictions that was put in place in the requirements on banks 2M, 2L, 2N (other than the ones mentioned in the KDB )

    On quartus 19.4 , probably I will check it later , as the KDB mention 19.1 and below, but i suspect additional requirements been put in place as well.

    Thanks

    Regards

    Kian

KianHinT_altera's avatar
KianHinT_altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,

Sorry for the delay in getting back to you. Just a status update on my investigation side, unfortunately still have issues on the pin placements

1. Able to replicate the same observation as you posted in the thread.

2. Found out that there is a KDB on this issue (https://www.intel.com/content/www/us/en/support/programmable/articles/000086902.html)

Apparently Quartus 19.1 and below have issues on the pinout restriction detection thus compilation will always pass.

What have been tested so far

1. Multiple Quartus version (20.1, 23.1, 24.1) to test the fitter to see any differences on the issue. All result with the same error.

2. Check the pins that are mentioned in the KDB (PLL and RZQ) and looks like it is already in bank 2M. Suspect other pin placement restriction.

3. Terasic website on newer designs able to compile on 24.1 but without EMIF HPS or the GHRD project (tested few designs)

3. Remove all pin assignments for DDR4A and let fitter to decide which pins to utilize . Result in different error where fitter unable to fit all the pins with the region constraints.

4. Manually remove pin assignments that were reported error by fitter tool and let fitter reassign the pins during compilation each time but eventually fitter still fails in the assignment.

Ongoing:

1. Looking at the pin placement restriction based on the KDB documentation and comparing to the Terasic user manual.

2. Engaging with EMIF expert to check on the DDR pin placement

Thanks

Regards

Kian