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Altera_Forum
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17 years ago

Strange synthesis result , getting crazy

I am new to VHDL. I am using Quartus II v.8 Web edition for synthesis.For several days i stuck at the following simple code.:( LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY clock ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Now i understand why my code was gerenating abnormal RTL.I created a dependency on the hour signal and the problem solved.

Many Many thanks.I was stuck at this problem for more than a week.