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Altera_Forum
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17 years ago

Strange synthesis result , getting crazy

I am new to VHDL. I am using Quartus II v.8 Web edition for synthesis.For several days i stuck at the following simple code.:( LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY clock ...
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Altera_Forum
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17 years ago

The synthesis tool recognizes that no output depends on the "hour" variable and synthesizes it away.

The only input for the trigger output in the code you are evaluating is the minute signal, which is independent from the hour signal. So the hour does not need to be counted.

If you create a dependency on the hour signal, lets say set the output to 1 in a specific hour only, then the hour will result in a register as well.

Regards,

Lokla