Strange synthesis result , getting crazy

I am new to VHDL.

I am using Quartus II v.8 Web edition for synthesis.For several days i stuck at the following simple code.:(

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY clock IS

PORT

(

clk_in : IN STD_LOGIC;

triger : OUT STD_LOGIC

);

END clock;

ARCHITECTURE clock_architecture OF clock IS

BEGIN

PROCESS(clk_in)

variable second : INTEGER RANGE 0 TO 59:=0;

variable minute : INTEGER RANGE 0 TO 59:=0;

variable hour : INTEGER RANGE 0 TO 23:=0;

variable interval : INTEGER RANGE 0 TO 9:=0;

variable outtriger :STD_LOGIC :='0';

BEGIN

if(clk_in'event and clk_in='1') then

if second < 59 then

second:=second+1;

else

second:=0;

if minute <59 then

minute:=minute+1;

if interval<9 then

interval:=interval+1;

outtriger:='0';

else

interval:=0;

outtriger:='1';

end if;

else

minute:=0;

if hour<23 then

hour:=hour+1;

else

hour:=0;

end if; --end of hour

end if; -- end of minute

end if; --end of second

end if; -- end of clk'event

triger <= outtriger;

END PROCESS;

END clock_architecture;

When i watch the RTL after synthesis all the variable second, minute, interval converts to registers but i didn't find any register for hour.(I attached the RTL with this thread).But if i remove following code l can find the register representing hour in RTL.

if interval<9 then

interval:=interval+1;

outtriger:='0';

else

interval:=0;

outtriger:='1';

end if;

Plz ...plz ...plz help me if you can.:mad:

Thanks in Advanced

Raisul

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