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Altera_Forum's avatar
Altera_Forum
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17 years ago

Strange Modelsim simulation result (undefined).

I got a strange simulation result. Asserting Output in the simplest way MostSignificant(MSA) <= VectorOnes (MSA); -- MostSignificant(MSA) is output ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Dear Vernmid

Thank you for your answer.

When I put the simple assignment in the process as you suggest I got in the simulation undefined in the two first cycles and amazing in the other cycles the value of MostSignificant(MSA) was as the VectorOnes (MSA) in the previous cycle.

I know it shouldn't happen according to VHDL instruction.

In all the versions MostSignificant(MSA) is assigned only once.

My amazement is because according to VHDL I shouldn't get any problem in both versions when the assignment is out the process and in the process.

Best Regards

Rami