--RealCaseGenericDontCare.vhd
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:42:21 07/09/2008 
-- Design Name: 
-- Module Name:    CaseDontCare - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY CaseGenericDontCare IS
	GENERIC
	(
		MSA	: integer:= 	7
	);
	PORT
	( 
	 VectorOnes         : IN   STD_LOGIC_VECTOR(MSA downto 0);
	 MostSignificant    : OUT STD_LOGIC_VECTOR(MSA downto 0)
	);
END CaseGenericDontCare;


ARCHITECTURE RamTel OF CaseGenericDontCare IS


BEGIN
--MostSignificant(MSA) <= VectorOnes (MSA);

PROCESS (VectorOnes)
Variable Exsist : STD_LOGIC ;
Variable MostSignificantMSA : STD_LOGIC ;

BEGIN
MostSignificantMSA    := VectorOnes (MSA);
MostSignificant(MSA)  <=    MostSignificantMSA;

FOR J in 0 TO (MSA-1) LOOP
Exsist 	 := '0';
 FOR i in (MSA) DOWNTO (MSA-j) LOOP
	IF (VectorOnes(i)	 = '1' ) Then
   Exsist := '1';
   END IF;
 MostSignificant(MSA-j-1) <= (Not Exsist) AND VectorOnes(MSA-j-1);
END LOOP;
END LOOP;
	



END PROCESS;
END RamTel;